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SC660E
SMBus System Clock Buffer for Mobile Applications
Features
* 10 output buffers for high clock fanout applications * Each output can be internally disabled for EMI and power consumption reduction. * Separate power supply for each group of 2 clock outputs for mixed voltage application. * < 250ps skew between output clocks. * 28-pin SSOP package for minimum board space * Single output Tristate pin for testability
Product Description
The device is a high fanout system clock distributor. Its primary application is to create the large quantity of clocks needed to support a wide range of clock loads that are referenced to a single existing clock. Loads of up to 30 pF are supported. Primary application of this component is where long traces are used to transport clocks from their generating devices to their loads. The creation of EMI and the degradation of waveform rise and fall times is greatly reduced by running a single reference clock trace to this device and then using it to regenerate the clock that drives shorter traces by using the SC660 to generate the clocks at the target devices EMI is therefore minimized and board real estate is saved.
Block Diagram
VDDB
Pin Configuration
SDRAM(0:1)
SDRAM(2:3)
SDRAM4 FIN SDRAM5 VDD
SDATA SCLOCK OE
I2C
SDRAM(6:7) SDRAM(8:9)
VDDB SDRAM0 SDRAM1 VSS VDDB SDRAM2 SDRAM3 VSS FIN VDDB SDRAM4 VSS VDD SDATA
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDDB SDRAM9 SDRAM8 VSS VDDB SDRAM7 SDRAM6 VSS OE VDDB SDRAM5 VSS VSS SCLOCK
Rev 1.0, December 06, 2006
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
Page 1 of 5
www.SpectraLinear.com
SC660E
Pin Description
Pin No. 9 2,3,6,7,11,18,22,23 ,26,27 20 Name FIN Sdram(0:9) OE PWR VddB I/O I O I Type PAD BUF1 PAD Description This pin is connected to the input reference clock. This clock must be in the range of 10.0 to 100.0 Mhz. Low skew output clocks. Buffer Output Enable pin. This pin is low it is used to place all output clocks (CLK1:10) in a tri state condition. This feature facilitates in production board level testing to be easily implemented for the clocks that this device produces. Has internal pull-up resistor. Serial Data for SMBus control interface. This pin receives data streams from the SMBus bus and outputs an acknowledge for valid data. Serial Clock for SMBus control interface. Ground pins for clock output buffers. These pins must be returned to the same potential to reduce output clock skew. Power for output clock buffers. Pin for device core logic.
14
Sdata
Vdd
I/O
PAD
15 4, 8, 12, 16, 17, 21, 25 1, 5, 10, 19, 24, 28 13
Sclock Vss VddB Vdd
Vdd
I PWR
PAD -
-
PWR PWR
Maximum Ratings[1]
Input Voltage Relative to VSS:................................VSS-0.3V Input Voltage Relative to VDDQ or AVDD: ........... VDD+0.3V Storage Temperature: ................................. -65 C to + 150 C Operating Temperature:.................................... 0 C to +85 C Maximum Power Supply: ................................................ 3.5V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS<(Vin or Vout)Note: 1. The voltage on any input or I/O pin cannot exceed the power pin during the power-up. Power supply sequencing is NOT required.
Rev 1.0, December 06, 2006
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SC660E
2-Wire SMBus Control Interface
The 2-wire control interface implements a write only slave interface. The device cannot be read back. Sub-addressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. The 2-wire control interface allows each clock output to be individually enabled or disabled. During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to indicate the start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of a data transfer cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer cycle is a 7-bit address with a Read/Write bit as the LSB. Data is transferred MSB first. The device will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low) signal on the SDATA wire following reception of each byte. The device will not respond to any other control interface conditions. Previously set control registers are retained.
Serial Control Registers
Following the acknowledge of the Address Byte, two additional bytes must be sent: 1. "Command Code " byte, and 2. "Byte Count" byte. Although the data (bits) in the command is considered "don't care"; it must be sent and will be acknowledged. After the Command Code and the Byte Count have been acknowledged, the sequence (Byte 0, Byte 1, and Byte 2) described below will be valid and acknowledged.
Byte 0: Function Select Register (1 = enable, 0 = Stopped)
Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Pin# 7 6 3 2 reserved reserved reserved reserved SDRAM3 (Active = 1, Forced low = 0) SDRAM2 (Active = 1, Forced low = 0) SDRAM1 (Active = 1, Forced low = 0) SDRAM0 (Active = 1, Forced low = 0) Description
Byte 1: Clock Register (1 = enable, 0 = Stopped)
Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Pin# 27 26 23 22 Description SDRAM9 (Active = 1, Forced low = 0) SDRAM8 (Active = 1, Forced low = 0) SDRAM7 (Active = 1, Forced low = 0) SDRAM6 (Active = 1, Forced low = 0) reserved reserved reserved reserved
Byte 2: Clock Register ( 1 = enable, 0 = Stopped )
Bit 7 6 5 4 3 2 1 0 @Pup 1 1 0 0 0 0 1 1 Pin# 18 11 Description
SDRAM5 (Active = 1, Forced low = 0)
SDRAM4 (Active = 1, Forced low = 0) Not Used Not Used Not Used Not Used Not Used Not Used
Rev 1.0, December 06, 2006
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SC660E
Electrical Characteristics
Parameter VIL VIH IIL IIH VOL VOH Ioz Idd66 Idd100 Isdd ISC TIR Static Supply Current Short Circuit Current Input Rise Time Description Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage IOL = 40mA Output High Voltage IOH = 30mA Tri-State leakage Current Dynamic Supply Current Min. 2.0 -66 2.4 25 2.4 Typ. Max. 0.8 66 0.4 10 160 220 4 Units Vdc Vdc A A Vdc Vdc A mA mA mA mA nS Input frequency = 66 Mhz - All outputs on and at 30 pF load Input frequency 100 Mhz - All outputs on and at 30 pF load All outputs disabled no input clock 1 output at a time - 30 seconds .8 to 2.4 volts All Outputs (see buffer spec) All Outputs Using 3.3V Power (see buffer spec) Conditions
-
VDD = VDD1 thru VDD5 =3.3V 5%, , TA = -40C to +85C
Switching Characteristics
Parameter tSKEW tSKEW TJCC Description Output Duty Cycle Buffer out/out Skew All Buffer Outputs Buffer input to output Skew Jitter Cycle to Cycle [2] Jitter Absolute (Peak to Peak)[2] Min. 45 2.0 Typ. 50 4.0 Max. 55 250 5.0 50 150 Units % pS nS pS pS @ 35 pF loading @ 35 pF loading Conditions Measured at 1.5V (50/50 in) 35 pF Load Measured at 1.5V
VDD = VDD1 thru VDD5 =3.3V 5%, , TA = -40C to +85C
TB40_ Type Buffer Characteristics (All Clock Outputs)
Parameter IOHmin IOHmax IOLmin IOLmax Zo TRFmin TRFmax Description Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Dynamic Output Impedance Rise/Fall Time Min Between 0.4 V and 2.4 V Rise/Fall Time Max Between 0.4 V and 2.4 V Min. 30 75 30 75 8 Typ. Max. 39 109 40 103 15 1.33 1.33 Units mA mA mA mA Ohms nS nS Vout = 1.5V Vout = 0.4 Vout = 1.2V 66 and 100 MHz 30 pF Load 30 pF Load Conditions Vout = VDD - .5V
VDD = VDD1 thru VDD5 =3.3V 5%, , TA = -40C to +85C
Note: 2. This jitter is additive to the input clock's jitter.
Rev 1.0, December 06, 2006
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SC660E
Ordering Information
Part Number SC660EYB 28-pin SSOP Package Type Product Flow Commercial,-40 to 85 C
Package Diagrams
28-Lead (5.3 mm) Shrunk Small Outline Package O28
14 1.14 1 1.14 DIA. PIN 1 ID.
1.14 7.50 8.10
DIMENSIONS IN MILLIMETERS MIN. MAX.
15 10.00 10.40
28
SEATING PLANE 0.65 BSC.
.235 MIN. GAUGE PLANE 2.00 MAX. 1.65 1.85 0.05 0.21 0.25
0 MIN.
0.10
0.22 0.38
5.00 5.60 1.25 REF. 0.55 0.95
0-8
51-85079-*C
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Rev 1.0, December 06, 2006
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